Published
by Olivier Mathieu, Market Development Manager
Advanced Electronics Solutions
While silicon is the most common element used for power semiconductors, copper is the most popular choice for conductor traces on printed circuit boards (PCBs) and ceramic substrates due to its electrical conductivity. Copper is a well-established material for base plates and heat sinks because of its thermal conductivity. Furthermore, it has become important for the metallization and interconnection of power devices. The ever-growing power density, current carrying capability and reliability requirements are factors to why copper is already widespread in the industry. Copper is readily available, relatively inexpensive, and not likely to disappear anytime soon.
Copper versus Aluminum
Aluminum is the most popular alternative to copper, depending on the application. For example, in heat sinks, aluminum is the preferred material because it is less expensive and lighter than copper. However, for certain applications when higher heat conductivity outweighs the available weight savings, copper is a more desirable alternative. At room temperature, copper has a thermal conductivity of 400 W/m-K, whereas aluminum´s conductivity is 235 W/m-K. Consequently, all other factors alike, a heat sink made of copper dissipates more heat than an aluminum heat sink. Thus, numerous power modules with integrated copper pin fin heat sinks have been accepted by the market and are successfully operating in the field of hybrid and electric vehicles today.
Aluminum and its alloys are widely-used for chip metallization. They exhibit a low electrical resistance and an excellent adhesion on silicon and silicon oxide layers. Despite that, copper metallization has been introduced to replace aluminum by taking advantage of its lower resistivity and higher thermal conductivity. Lower resistivity allows higher current flow per unit area with less joule heat generation; while higher thermal conductivity dissipates heat more efficiently. These two distinct advantages for copper enable greater current flows and miniaturization. Unfortunately, copper cannot be structured as easily as aluminum in dry etching processes. Therefore, not all chips come with copper metallization. Moreover, cost and stress issues are limiting the copper metallization thickness between 5 μm to 10 μm, though thicker layers would certainly support higher current drivability, higher heat capacity and heat dissipation. Although, some workarounds are possible as demonstrated by Danfoss with its bond buffer technology: by sintering a thin copper foil on top of the chips.
Reliability is another driving factor to establish copper as a standard chip metallization. The main cause for failure in state-of-the-art power modules is the bond-wire lift-off. As a consequence, new solutions to interconnect multiple chips in a power module have been developed to replace conventional aluminum wires. Many solutions rely on copper material in different shapes and geometries: wires, ribbons, pillars, clips or lead frames which can be soldered, sintered or welded on the chips. Other solutions include planar interconnecting and chip embedding technologies where top side electrical contacts are connected due to filled copper vias.
Heavy copper is no longer heavy enough
Conductor traces in the inner and outer layers of PCBs and ceramic substrates are predominantly made of copper, even though some substrates exist with aluminum metallization.
Copper thickness can be specified as the weight of copper in ounce per square foot (oz/ft²). Most commercially available PCBs are manufactured for low power applications with copper traces made of copper weights ranging from 0.5 oz/ft² (18 µm) up to 3 oz/ft² (105 µm). For higher power applications, heavy copper circuits can be manufactured with copper weights between 4 oz/ft² (140 µm) and 20 oz/ft² (686 µm). Copper weights above 20 oz/ft² are also possible and are referred to as extreme copper.
Particularly, Direct Bonded Copper (DBC) and Active Metal Brazed (AMB) substrates are used to attach and connect multiple power devices in parallel to a module to achieve the required power rating for a given application. These substrates are available with typical copper thickness ranging from 127 µm up to 800 µm. However, the trend for miniaturization holds true for power modules, too. Hence, module makers are pushing the limits of semiconductor and packaging technologies, in order to further increase the output power in existing or even smaller footprints. Moreover, as the increase in performance should not impact cost and reliability, substrates and base plate or heat sink have to be attached with new joining technologies or even better integrated in one single component. This eventually leads to the development of substrates with copper layers thicker than 1 mm.
Generally, thick copper layers are manufactured with the same wet chemical etching process as standard copper layers. Because of its isotropic characteristic, wet chemical etching becomes inadequate for patterning thick copper layers, since it results in wide trenches between conductor tracks, and customers require narrow trenches to reduce the footprint of their modules. Thus, specialized structuring techniques have to be developed instead to achieve narrow gaps, straight sidewalls and negligible undercuts.
Development projects have been initiated and are ongoing at Rogers PES to deliver market driven solutions that fit your specific needs. As an example, multilayer ceramic substrates and enhanced DBC substrates have been presented at the last PCIM exhibition and there are many more new products to come.
As a manufacturer of metallized ceramic substrates, Rogers Corporation and the PES team is available to help you as a development partner. Do you have any question or require some support with the design and selection of a suitable substrate for your application? Please contact us, if you need assistance.
Related Products:
curamik Ceramic Substrates
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Olivier's Twist Blog, Aerospace & Defense, Automotive & EV/HEV, General Industrial, Major Appliances, Rail
Published on Aug 01, 2019